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All of the accoutrement you charge to assignment with the FPGA Arduino — the Vidor — are now in the wild!

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We appear beforehand that a alternation of French blog posts assuredly showed how all the pieces fit calm to affairs the FPGA on the Arduino MKR4000 Vidor board. Of course, I wasn’t agreeable to aloof apprehend the Google translation, I had to breach out the lath and try myself.

I created a actual simple amateur template, a apparatus in C to do the bitstream conversion, required, and abiding it all calm in one place. Here’s how you can use my amateur kit to do your own FPGA designs application the Vidor. I’m activity to accept you apperceive about FPGA basics and Verilog. If you don’t, why not analysis out the FPGA cossack camps first?

The aboriginal affair you’ll appetite to do is grab my GitHub repo. You’ll additionally charge the Arduino IDE (a contempo copy) and Intel’s Quartus software. Inside, you’ll acquisition three directories, two of which accommodate hardly adapted copies of aboriginal Arduino files. But afore you alpha digging in, let’s get the high-level overview of the process.

The FPGA onboard the Vidor is an Intel/Altera accessory so to configure it, we’ll use Quartus. Usually, Quartus handles aggregate including programming the device, but we can’t use it for that with the Vidor. Instead, we will accept to acquaint the CPU how we appetite the FPGA configured and it will do it for us as allotment of our Arduino affairs (I absolutely abhorrence adage sketch).

Quartus (see below) will booty our Verilog files and actualize a ttf book that represents the agreement bitstream. This is aloof an ASCII argument book abounding of decimal numbers. Unfortunately, the way the Vidor is set up, it needs the numbers bit antipodal at the byte level. That is, 01 in the ttf book needs to be 80 hex beatific to the FPGA.

Arduino food a Java chic book to do the task, but I got balked because the chic book bare Java 11 and I didn’t appetite to put it on every apparatus I use, so I aloof rewrote it in C. It is accessible abundant to anchorage the algorithm, though. In the carapace subdirectory, I accept addition archetype accomplishing application awk.

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Once you accept this beck of numbers, you can accommodate it in an Arduino account with some boilerplate to accredit the FPGA and amount it. The accepted affairs includes the book app.h which is aloof the achievement of the about-face program. There’s no C cipher in it, aloof comma-separated numbers that the capital cipher will stick in an arrangement at compile-time. Beyond that, it is a accustomed Arduino affairs and you can do what you like. Upload it and you’ll get the CPU and FPGA programmed all in one go.

There is one caveat. The FPGA cipher has a top-level block with lots of I/O pins authentic and the agnate constraints. You should be actual accurate not to change these or adapt the pin constraints. If you drive a pin that’s already an output, for example, you could do absolute abuse to the board. Because all the pins are shared, you accept the aforementioned botheration with the Arduino pins, too. If you are active an achievement pin with the FPGA, you shouldn’t try to drive it with the CPU also. However, as you will see, it is altogether accomplished to accept the FPGA account a pin from the CPU or carnality versa. That’s acceptable because it gives us a way to accelerate abstracts aback and alternating amid them.

I capital article simple, and I didn’t appetite to accidentally adapt the Arduino boilerplate Verilog. You could instantiate a Verilog module, but this would crave casual all the I/O pins into the bore or modifying the aboriginal cipher every time, both of which I capital to avoid.

My acknowledgment was to use the Verilog `include charge central the boilerplate. That way your cipher has admission to aggregate the capital bore has, but you don’t accept to change the capital module. The abandoned downside is that Quartus has a acute abridge affection that can’t amount out back abandoned an accommodate book changes. So it wasn’t recompiling back I fabricated changes. I angry that affection off in the Quartus options, so if you aces up my archetype project, you won’t accept any problems.

Here’s my archetype user.v:

In the absolute file, I larboard a lot of comments in that explains what all the capital bore has that you can use. But the aloft is the alive part. I ascertain a 28 bit counter. The bMKR_D arrangement is the agenda ports for the Arduino and I’m application pin 6 and 5 as an achievement and an input, respectively.

The accredit account says, in English, If D5 is high, affix the 27th bit of the adverse to the LED. If it is low, affix the 21st bit. The blow of the cipher aloof makes the adverse countdown. I reload the adverse alike admitting it would artlessly cycle over in case you appetite to accomplished tune it to a altered frequency.

As the adverse runs, bit 27 will toggle almost slowly, but bit 21 will be a acceptable bit faster — that’s aloof how a adverse is. So by alteration D5 you can accomplish the LED blink apathetic or fast.

As Verilog goes, this isn’t actual complicated or alike useful, but it is simple and shows that we can allotment abstracts with the CPU in both directions. If you accessible the archetype activity in Quartus, all you absolutely charge to do is accomplish any changes to user.v you like, add any added files you appetite to use and double-click the Abridge Design assignment (see left). If you get a acknowledged compile, you’ll acquisition the ttf book in the output_files directory. That’s the book you charge to action with either the Java program, the C program, or the awk script. Either way, aggregate the achievement as app.h and put it in the aforementioned agenda as your Arduino code.

On the account side, you charge to leave the arrangement cipher abandoned back it turns on the FPGA clock, amid added things. You’ll apprehension it additionally includes app.h and uses a book alleged jtag.c to acquaint with the FPGA. I didn’t choose the Arduino cipher into its own accommodate because you apparently accept to change the bureaucracy function, and accomplish changes in all-around space, but that could be abiding (perhaps accomplish bureaucracy alarm cpu_setup and bend alarm cpu_loop or something).

If you appetite to abolish the audience genitalia of the blink-sketch file, you can get rid of:

I larboard the blunt cipher in the EmptySketch directory. Note in the audience code, admitting that SPEED is an output. This is set to D5, which is an ascribe to the FPGA. By the aforementioned token, FPGALED corresponds to D6 and allows the CPU to apprehend the accompaniment of the LED output.

You will charge an LED and bottomward resistor on pin 6 unless you appetite to watch with a ambit or a meter. I consistently accumulate some LEDs with congenital 5V bottomward resistors handy, and alike at 3.3V it was affluence bright. With one of those, you can aloof stick the affairs appropriate into the attack atrium on the board. Don’t try that with a approved LED, though!

Once you run the sketch, you can accessible the consecutive adviser or any terminal at 9600 baud. There will be a bulletin adage you can columnist any key to change the blink rate. Of course, back the consecutive adviser doesn’t acquiesce you to columnist keys exactly, you’ll accept to access article and hit access (set “No band ending” at the basal of the adviser screen), but on a absolute terminal, any appearance columnist should do it.

The capital cipher is appealing simple:

In the loop, if consecutive abstracts appears, we aloof toggle the achievement activity to the FPGA. We additionally sample the LED achievement on every pass. If it has afflicted from the aftermost time, we address the new accompaniment to the terminal and again amend the accompaniment so we don’t flood the awning with again characters. A lot of the cipher is aloof tracking back we’ve accounting abundant to alpha a new line.

I capital to get aggregate you bare in one abode and an archetype that would be accessible to chase yet appearance the analytical alive parts. It would be accessible abundant to use the aggregate I/O pins to do SPI, for example, and again you could barter abstracts with the FPGA absolutely easily. Don’t balloon there’s Arduino IP (intellectual property; array of library subroutines for FPGAs) in the IP directory, too, if you appetite to use it.

Now you aloof charge a activity abstraction that makes faculty for an FPGA. Our claimed admired would be a argumentation analyzer. The CPU can allocution to the PC, set up triggers and again let the FPGA do the bedraggled assignment of award the activate and autumn abstracts as fast as possible. If you appetite article beneath ambitious, it is actual simple to actualize absolutely free PWM outputs on an FPGA. We could see this actuality accessible for robotics or apparatus ascendancy area you appetite a actual accelerated arrangement of outputs after CPU action or overhead.

Of course, not every activity has to accomplish sense. If you are aloof absent to apprentice about FPGAs there are affluence of projects you could do with a CPU but are accessible abundant to body in an FPGA (the archetypal cartage ablaze comes to mind). Of course, with the Vidor you accept an befalling to use a alloy of FPGA cipher and CPU code, which is affectionate of the point.

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