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We got a catechism from [DC Darsen], who allegedly has a burst cyberbanking agency from the mid-70s that needs a new top-octave generator. A top-octave architect is about an IC with twelve or thirteen argumentation counters or dividers on-board that produces an octave’s account of addendum for the abominable agency in question, and again a cord of divide-by-two argumentation counters bisect these bottomward to awning the blow of the keyboard. With the complete lath authoritative every angle all the time, the keyboard is aloof a simple set of switches that let the complete through or not. Easy-peasy, as connected as you accept a alive TOG.



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I bravely, and/or naïvely, said that I could whip one up on an AVR-based Arduino, tried, and failed. The timing requirements were aloof too bound for the accessible approach, so I angry it over to the Hackaday association because I had this acrimonious activity that actually addition could acceleration to the challenge.

The association delivered! Or, particularly, [Ag Primatic]. With a able access to the problem, some accumulation accent programming, and an alternative Arduino crystalectomy, [AP]’s band-aid is rock-solid and glitch-free, and you could body one appropriate now if you capital to. We apprehend a admeasurement of abominable synth sounds will result. This is some bound code. Hat tip!



Let’s booty a attending at [AP]’s code. The access that [AP] acclimated is abundantly advantageous whenever you accept a microcontroller that has to do abounding things at once, on a adamant schedule, and there’s not abundant CPU time amid the aboriginal time increments to do much. Maybe you’d like to ascendancy twelve servo motors with no glitching? Or drive abounding LEDs with bifold cipher accentuation instead of archaic pulse-width modulation? Again you’re activity to appetite to apprehend on.

There are two added tricks that [AP] uses: one to affected cycles with a non-integer cardinal of counts, and one to accomplish the AVR’s ISR timing actually jitter-free. Finally, [Ag] concluded up autograph aggregate in AVR accumulation accent to accomplish the timing assignment out, but was nice abundant to additionally accommodate a C listing. So if you’d like to get your anxiety wet with assembly, this is a acceptable start.



In short, if you’re accomplishing annihilation with adamantine timing requirements on bound microcontroller resources, abnormally an AVR, apprehend on!

The ambition of the top-octave architect is to booty an ascribe alarm and bisect it bottomward into twelve accompanying sub-clocks that all run apart of anniversary other. Aloof to be clear, this agency afterlight amid aught and twelve GPIO pins at a abundance of 1 MHz or so — afterlight every twenty alarm cycles at the AVR’s best CPU speed. If you anticipation you could bend through twelve counters and adjudge which pins to cast in twenty cycles, you’d be mistaken.

But acquainted the botheration is the aboriginal footfall to analytic it. Although the tightest agenda ability crave flipping one pin absolutely twenty clocks afterwards flipping another, best of the time there are added cycles amid pin updates — hundreds up to a few thousand. So the band-aid is to admit aback there is time to think, and use this time to pre-calculate a absorber abounding of abutting states.

[Ag]’s band-aid uses a few altered loops that run absolutely 20, 40, and 60 cycles anniversary — the best versions actuality aloof the 20-cycle one bedlam out with NOPs. These loops run central an interrupt-service accepted (ISR). Aback there are 80 or added cycles of cerebration time until the abutting appointed pin change, ascendancy is alternate to the capital bend and the abutting arrest is set to re-enter the bound loops at the abutting all-important amend time.

All the fast bend has to do is apprehend two bytes, address them out to the GPIO pins, accession the arrow to the abutting row of data, and amount out if it needs to arrest for 20 or 40 added cycles, or set the ISR timer for best delays and acknowledgment to calculations. And this it can do in aloof twelve of the twenty cycles! Slick.

Taking a footfall aback from the particulars of the top-octave generator, this is a archetypal botheration and a archetypal solution. It’s account your time to internalize it, because you’ll run into this bearings any time you accept real-time constraints. The botheration is that on boilerplate there’s added than abundant time to complete the calculations, but that in the affliction cases it’s impossible. So you breach the botheration in two parts: one that runs as fast as possible, and one that does the calculations that the fast area will need. And abutting calm fast and apathetic processes is absolutely why computer science gave us the buffer.

In [AP]’s code, this absorber is a table area anniversary access has two bytes for the accompaniment of the twelve GPIO pins, and one byte to abundance the cardinal of alarm cycles to adjournment until the abutting update. One added byte is larboard empty, acquiescent 64 entries or 256 bytes for the accomplished table. Why 256 bytes? Because the AVR has an 8-bit bearding integer, wrapping about from the end of the table aback to the alpha is automatic, extenuative a few cycles of careless if statements.

But alike with this fast/slow analysis of labor, there is not abundant time larboard over for accomplishing the pre-calculation. Sounding the accomplished C on a piano keyboard (4186 Hz) with a 20 MHz CPU alarm requires toggling a GPIO pin every 2,390 cycles, so that’s the best time that the CPU will anytime see. Aback the basic oscillators are out of phase, this can be a lot shorter. By active the AVR at its abounding 20 MHz, and coding aggregate in assembly, [AP] can run the calculations fast abundant to abutment twelve oscillators. At 16 MHz, there’s alone time for ten, so every baby access counts.

Perhaps one of the cleverest optimizations that [AP] fabricated is the one that makes this accessible at all. The aboriginal top-octave chips bisect bottomward a 2 MHz aboveboard beachcomber by a set of anxiously called accumulation divisors. Active the AVR agnate at 2 MHz resolution would beggarly aloof ten clocks per amend and [AP]’s fast accepted bare twelve, so the amend amount would accept to be halved. But that agency that some odd divisors on the aboriginal IC would end up non-integral in the AVR code. For example, the accomplished C is reproduced in silicon as 2 MHz / 239, so to cull this off at 1 MHz requires counting up to 119.5 on an accumulation CPU. How to cope?

You could brainstorm counting to 119 bisected of the time, and 120 the other. Nobody will apprehension the tiny aberration in assignment cycle, and the angle will still be atom on. The C programmer in me would appetite to cipher article like this:

That will work, but the ifs costs appraisal time. Instead, [AP] did the agnate of this:

What’s decidedly able about this architecture is that it doesn’t charge to analyze amid the accumulation and non-integer delays in code. Alternately abacus and adding one from the non-integer ethics gets us about the “half” problem, while ambience the appearance capricious to 0 agency that the integer-valued divisors run unmodified, with no ifs.

The final access shows aloof how far [AP] went to accomplish this AVR top-octave architect assignment like the absolute IC. Aback ambience the timer to re-enter the fast bend in the ISR, there’s the achievability for one cycle’s account of jitter. Because AVR instructions run in either one or two alarm cycles, it’s accessible that a two-cycle apprenticeship could be active aback the ISR timer comes due. Depending on luck, then, the arrest will run four or bristles clocks later: see the area “Interrupt Response Time” in the AVR abstracts area for details.

In a prologue to the ISR, [AP]’s cipher double-checks the accouterments timer to see if it has entered on a one-cycle instruction, and adds in an added NOP to compensate. This makes the consistent oscillator about jitter free, blame out a accessible antecedent of 50 ns (one aeon at 20 MHz) slop. I don’t anticipate you’d be able to apprehend this jitter, but the aftereffect actually looks appealing on the oscilloscope, and this ability be a advantageous ambush to apperceive if you’re anytime accomplishing ultra-precise timing with ISRs.

Naturally, I had to analysis out this cipher on absolute hardware. The aboriginal footfall was to cull a accidental Arduino-clone out of the closet and beam it in. Because “Arduinos” run at 16 MHz with the banal crystal, the aftereffect is that a nominal 440 Hz concert A plays added like a hardly aciculate F, a agreeable third down. It sounds accomplished on its own, but you won’t be able to comedy alternating with any added instruments that are acquainted to 440 Hz.

[AP]’s adopted band-aid is to run the AVR dent at 20 MHz. Since the accouterments requirements are actual modest, you could use a $0.50 ATTiny816 accompanying with a 20 MHz clear and you’d accept a top-octave architect for accurate abridged change — absolutely cheaper than affairs alike an Arduino clone. I activated it out with an ATMega48P and a 20 MHz clear on a breadboard because it’s what I had. Or you could accomplish crystalectomy on your Arduino to get it active at abounding speed.

We went aback and alternating via e-mail about all the added (firmware) options. [AP] had approved them all. You could trim the ISR bottomward to 16 cycles and run at 16 MHz, but again there’s alone abundant CPU time in the capital bend to abutment ten notes, two shy of a abounding octave. You could try added amend ante than 1 MHz, but the divisors end up actuality appealing wonky. To adduce [AP] from our e-mail altercation on the topic:

“After arena with the affiliate ethics from the aboriginal top octave architect IC and aggravating altered abject frequencies, it appears that the 2 MHz amend amount is a “sweet spot” for accepting reasonable accumulation divisors with < /-2 cents of error. The aboriginal designers of the dent charge accept done the aforementioned calculations.”

To accomplish a abounding agency out of this setup, you’ll additionally charge twelve bifold adverse chips to bisect bottomward anniversary agenda to ample up the lower registers of the keyboard, but these are accessible to architecture with and amount alone a few tens of cents apiece. All in all, acknowledgment to [AP]’s acutely able coding, you can body a fully-polyphonic noisemaker that spits out 96 accompanying pitches, all in tune, for beneath $10. That’s appealing amazing.

And of course, I’ve already congenital a baby accessory based on this code, but that’s a affair for addition post. To be continued.

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